The invention relates to a phase adjusting method and apparatus of a clock and, more particularly, to a phase adjusting method and apparatus of a clock which is suitable for use in an electronic computer, a communicating apparatus, or the like of a short machine cycle time that has a clock system having a phase adjusting circuit to reduce a clock skew, an electronic apparatus using such a phase adjusting method, and a semiconductor integrated circuit for embodying the phase adjusting method.
Generally, to reduce the machine cycle time of a large scale computer or the like, it is necessary to minimize the skew of a clock signal of a whole system. Hitherto, to minimize the skew of the clock signal, a method of adjusting the phase of the clock signal is used.
However, a semiconductor device which is used in an electronic apparatus as well as a large scale electronic computer has a temperature dependency of a signal delay time. Therefore, a conventional technique which merely performs the phase adjustment has a problem such that after the phase of the clock signal was adjusted, when a variation in temperature change occurs among the devices in the apparatus, a clock skew is caused.
As a technique which can solve such a problem, for instance, there is known a technique disclosed in U. S. Pat. No. 5,043,596 assigned to Hitachi Ltd.
The above document teaches a method of intermittently executing the phase adjustment of a clock in a real time manner by switching a delay circuit while always detecting a temperature. The above method is effective to execute the severe phase adjustment in a real time manner in a system in which a temperature change of the device is severe during the operation of the apparatus. However, a temperature compensating circuit is complicated and a management of advanced LSI circuit manufacturing processes is necessary in order to raise the accuracy of the temperature detection. It is, therefore, difficult to realize such a conventional technique in a general large scale computer.